1. Field of the Invention
The present invention generally relates to a highspeed scanning type ratio receiver. More specifically, the present invention relates to a highspeed scanning type radio receiver capable of preventing erroneous interruptions of scanning operations caused by high frequency noises produced from a clock oscillator of a microcomputer, a local oscillator circuit used to a heterodyne reception, and other circuits.
2. Description of the Prior Art
In highspeed scanning type radio receivers for scanning channels at high speeds to perform channel selections, microcomputers are employed for control purposes. As clock oscillators used for microcomputers, such clock oscillators are widely utilized from which highspeed clocks are produced in order to scan channels at high speeds. Then, high frequency noises are generated from such highspeed clock oscillators. Further, when local oscillator circuits for heterodyne receptions are employed in highspeed scanning type radio receivers, high frequency noises are produced from the local oscillator circuits. Thus, these high frequency noises may cause erroneous interruptions of scanning operations during channel selections.
FIG. 1 represents a highspeed scanning type FM radio receiver with employment of frequency synthesizer type electronic tuning.
This FM radio receiver is arranged by an antenna 10, a radio receiving unit 12 containing a converter unit for converting a frequency of an FM radio signal received from the antenna 10 into an intermediate frequency thereof, a frequency discriminator 14 for converting a change in the intermediate frequencies of the intermediate frequency signals derived from the radio receiving unit 12, into a change in voltages, and a squelch circuit 16 for detecting whether or not the received signal is present based upon the output voltage from the frequency discriminator. The FM radio receiver further includes a window detector 22 for detecting whether or not a voltage corresponding to the center frequency of the intermediate frequency signal is output from the frequency discriminator 14, a audio frequency amplifier 18 for amplifying the output signal from the frequency discriminator 14, a speaker 20 for outputting the FM sound derived from the audio frequency amplifier 18, a frequency synthesizer 24 containing a phase-locked loop (PLL) circuit, a microcomputer (CPU) 26 for controlling operations of all circuit units, and a keyboard 28 for instructing the frequency synthesizer 24, and also a clock oscillator 30 for supplying clock signals to the CPU 26.
Typically, there are two scanning methods for such an FM radio receiver performed based upon response characteristics of the noise squelch circuit. The noise squelch circuit 16 compares the noise detecting voltage with the voltage "V.sub.TH " set by a squelch controller (not shown) to produce the squelch control signal (will simply be referred to as "SC signal" hereinafter) when the noise detecting voltage is lower than the set voltage "V.sub.TH ", as shown in FIG. 2.
That is, a first scanning method corresponds to the normal scanning method. While a certain channel is scanned, when both of the SC signal is supplied from the squelch circuit 16 to the CPU 26 and the window signal (will be simply referred to as "WD signal" hereinafter) is supplied from the window detector 22 thereto, it is assumed that a desired signal can be received in this scanned channel, thereby interrupt this channel scanning operation. In accordance with this first scanning method, since the SC signal has not so fast, or quick response, a lengthy search time is required.
To the contrary, a second scanning method can realize a high-speed scanning operation. As represented in FIG. 3, in addition to the SC signal, another signal (will be simply referred to as "SP signal" hereinafter) is produced by detecting such a time instant when a change in the noise detecting voltages tends to be decreased (namely, portion "A" indicated by a dotted line of FIG. 3). Both of these SP signal and SC signal are utilized for the channel scanning operation. That is, in a channel where the SP signal is detected, the SC signal and the WD signal are detected, whereas in a channel where no SP signal is detected, the searching operation is advanced to the next channel. As a consequence, the overall scanning operation can be performed at high speeds. It should be noted that such a second scanning method will be called as a "turbo-scanning method".
Referring now to FIG. 4, the normal scanning method of this FM radio receiver shown in FIG. 1 will be described. It should be noted that FIG. 4 represents an operation flow of the CPU 26 for executing the operation of the normal scanning operation.
During the normal channel scanning operation, the CPU 26 sends PLL data about a certain channel to the frequency synthesizer 24. The frequency synthesizer 24 synthesizes a preselected frequency based on the PLL data and then sends the synthesized frequency to the radio receiving unit 12. The radio receiving unit 12 mixes the synthesized predetermined frequency derived from the radio receiver 12 with the frequency of the FM signal received via the antenna 10 by this radio receiving unit 12, thereby converting the frequency of the FM signal into the desirable intermediate frequency. The resultant intermediate frequency signal derived from the radio receiving unit 12 is supplied to the frequency discriminator 14. Then, the frequency discriminator 14 converts the intermediate frequency of this intermediate frequency signal into the voltage in accordance with the frequency-voltage converting characteristic, and supplies the voltage to the squelch circuit 16 and the window detector 22. The squelch circuit 16 produces the SC signal when the noise detecting voltage becomes lower than the set voltage V.sub.TH. The window detector 22 produces the WD signal when the detection is made of the voltage corresponding to the center frequency of this intermediate frequency signal. In the normal scanning operation of FIG. 4, the CPU 26 starts an SC signal detecting timer (not shown in detail) so as to detect the SC signal derived from the squelch circuit 16 (step S1), thereby judging whether or not the SC signal is produced from the squelch circuit 16 (step S2). If no SC signal is detected and the SC detecting timer is not timed out (step S3), the scanning operation is returned to the previous step S2.
To the contrary, if the SC signal is detected at the step S2, then the CPU 26, judges whether or not the WD signal is produced from the window detector circuit 22 (step S4). When the window signal is detected, the CPU 26 makes such a judgement that the FM signal is received in this scanned channel, and cases this normal scanning operation. To the contrary, if no window signal is detected, then the CPU 26 sends the PLL data about the next channel to the frequency synthesizer 24 (step S5). When the SC signal detecting timer is brought into the time out state, the CPU 26 supplies the PLL data about the subsequent channel to the frequency synthesizer 24, so that the channel searching operation for the subsequent channel is commenced.
Referring now to FIG. 5, the above-described turbo-scanning method in the FM radio receiver will be described. FIG. 5 is a flow chart for explaining operations of the CPU 26 to execute the turbo-scanning method.
In the turbo-scanning operation, the CPU 26 starts a PLL (phase-locked loop) locking detection timer (step S1) and judges whether or not the PLL circuit of the frequency synthesizer 24 (step S2). If neither PLL locking operation is detected, nor the PLL locking detection timer is timed out (step S3), then the turbo-scanning process is again returned to the step S2. When the PLL locking operation (phenomenon) is detected at the step S2, an SP signal detection timer is commenced (step S4) to check whether or not the SP signal is detected (step S5). If the SP signal is not detected and the SP detection timer is not brought into the time out condition (step S6), then the turbo-scanning process is returned to the step S5.
At the step S5, when the SP signal is detected, the SC signal detection timer is started (step S7) to judge whether or not the SC signal is detected (step S8). When no SC signal is detected and the SC signal detection timer is not brought into the time out state (step S9), the turbo-scanning process is again returned to the step S8.
When the SC signal is detected at the step S8, a check is done whether or not the WD signal from the window detector circuit 22 is detected (step S10). If the WD signal is detected, then it may be judged a predetermined signal is received in this channel, so that the turbo-scanning operation is interrupted. If no WD signal is detected, then the PLL data about the next channel is supplied to the frequency synthesizer (step S11). At the steps S3, S6, S9, when the respective timers are timed out, the PLL data of the next channel is sent to the frequency synthesizer 24 (step S11).
To perform either the normal scanning, or the turbo-scanning at high speeds, the CPU 26 must be operated at high speeds. Therefore, high-speed clocks are required. In such a case, high frequency noises produced from the clock oscillator 30 may cause erroneous interruptions of the scanning operation. Also, in the receiver having the clock oscillator circuit, the clock oscillator circuit may function as a generating source for high frequency noises which similarly cause erroneous interruption of the scanning operation.